Information

GPIOx_PTOR field descriptions
Field Description
31–0
PTTO
Port Toggle Output
Writing to this register will update the contents of the corresponding bit in the PDOR as follows:
0 Corresponding bit in PDORn does not change.
1 Corresponding bit in PDORn is set to the inverse of its existing logic state.
47.2.5 Port Data Input Register (GPIOx_PDIR)
Addresses: GPIOA_PDIR is 400F_F000h base + 10h offset = 400F_F010h
GPIOB_PDIR is 400F_F040h base + 10h offset = 400F_F050h
GPIOC_PDIR is 400F_F080h base + 10h offset = 400F_F090h
GPIOD_PDIR is 400F_F0C0h base + 10h offset = 400F_F0D0h
GPIOE_PDIR is 400F_F100h base + 10h offset = 400F_F110h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PDI
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_PDIR field descriptions
Field Description
31–0
PDI
Port Data Input
Reads 0 at the unimplemented pins for a particular device. Pins that are not configured for a digital
function read 0. If the Port Control and Interrupt module is disabled, then the corresponding bit in PDIR
does not update.
0 Pin logic level is logic 0, or is not configured for use by digital function.
1 Pin logic level is logic 1.
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1184 Freescale Semiconductor, Inc.