Information

48.6.1 General Control and Status Register (TSIx_GENCS)
Addresses: TSI0_GENCS is 4004_5000h base + 0h offset = 4004_5000h
Bit 31 30 29 28 27 26 25 24
R
0
LPCLKS
LPSCNITV
W
Reset
0 0 0 0 0 0 0 0
Bit
23 22 21 20 19 18 17 16
R
NSCN PS
W
Reset
0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8
R
EOSF OUTRGF EXTERF OVRF 0 SCNIP
W
w1c w1c w1c w1c SWTS
Reset
0 0 0 0 0 0 0 0
Bit
7 6 5 4 3 2 1 0
R
TSIEN TSIIE ERIE ESOR
0
Reserved STM STPE
W
Reset
0 0 0 0 0 0 0 0
TSIx_GENCS field descriptions
Field Description
31–29
Reserved
This read-only field is reserved and always has the value zero.
28
LPCLKS
Low Power Mode Clock Source Selection.
This bit-field can only be changed if the TSI module is disabled (TSIEN bit = 0).
0 LPOCLK is selected to determine the scan period in low power mode
1 VLPOSCCLK is selected to determine the scan period in low power mode
27–24
LPSCNITV
TSI Low Power Mode Scan Interval.
This bit-field can only be changed if the TSI module is disabled (TSIEN bit = 0).
0000 1 ms scan interval
0001 5 ms scan interval
Table continues on the next page...
Chapter 48 Touch sense input (TSI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1195