Information

TSIx_SCANC field descriptions (continued)
Field Description
5
Reserved
This read-only field is reserved and always has the value zero.
4–3
AMCLKS
Active Mode Clock Source
00 LPOSCCLK
01 MCGIRCLK.
10 OSCERCLK.
11 Not valid.
2–0
AMPSC
Active Mode Prescaler
000 Input Clock Source divided by 1.
001 Input Clock Source divided by 2.
010 Input Clock Source divided by 4.
011 Input Clock Source divided by 8.
100 Input Clock Source divided by 16.
101 Input Clock Source divided by 32.
110 Input Clock Source divided by 64.
111 Input Clock Source divided by 128.
48.6.3 Pin Enable Register (TSIx_PEN)
Do not change the settings when TSIEN is 1.
Addresses: TSI0_PEN is 4004_5000h base + 8h offset = 4004_5008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
LPSP
PEN15 PEN14 PEN13 PEN12 PEN11 PEN10
PEN9 PEN8 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TSIx_PEN field descriptions
Field Description
31–20
Reserved
This read-only field is reserved and always has the value zero.
19–16
LPSP
Low Power Scan Pin
0000 TSI_IN[0] is active in low power mode.
0001 TSI_IN[1] is active in low power mode.
0010 TSI_IN[2] is active in low power mode.
0011 TSI_IN[3] is active in low power mode.
0100 TSI_IN[4] is active in low power mode.
0101 TSI_IN[5] is active in low power mode.
0110 TSI_IN[6] is active in low power mode.
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1200 Freescale Semiconductor, Inc.