Information

48.7.4.2 Error interrupt
The GENCS[EXTERF] is set in the case the capacitance result registers, TSICHnCNT, of
a TSI pin is either 0 or 0xFFFF, the two possible extreme values. The EXTERF flag
generates a TSI Error Interrupt request if the GENCS[ERIE] bit is set.
48.8 Application information
After enable the TSI module for the first time, it is highly recommended a calibration to
all the enabled channels by setting proper high and low threshold value for each active
channel. All the channel dedicated counter values can be read from each counter value
registers, software suite can then adjust the threshold based on these values.
Follow proper PCB layout guidelines for board design on electrode shapes, sizes, routes,
etc. Visit www.freescale.com/touch for application notes and reference designs.
48.8.1 TSI module sensitivity
The TSI module sensitivity is defined by the increment cause in the TSICHnCNT result
registers caused by a 1 pF delta in the electrode pin capacitance.
It is given by the following equation:
TSI
sensitivity
Iref * PS * NSCN
Cref
*
I
For the example provided, I
ref
= 2 µA, PS = 2; NSCN = 16, C
ref
= 1.0 pF and I =2 µA, the
TSI
sensitivity
= 0.03125 pf/count
48.9 TSI module initialization
This section provides the recommended initialization sequence for the TSI module.
Prior to enable TSI module by setting TSI_GENCS[TSIEN] bit, it is required to
configure other bits first. The pin enable registers are set to select which channels will be
sampled, the dual oscillators configuration bits are set in order to make the scan and
conversion more accurate. Also remember not to change the settings while TSI is
working in progress. To switch from different scan modes, for instance, it is required to
do a software reset to TSI by disabling and then enabling TSI_GENCS[TSIEN].
Application information
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1212 Freescale Semiconductor, Inc.