Information

The value shown adjacent to each state transition in this figure represents the value of TMS at the time
of a rising edge of TCK.
TEST LOGIC
RESET
RUN-TEST/IDLE
SELECT-DR-SCAN
SELECT-IR-SCAN
CAPTURE-DR
CAPTURE-IR
SHIFT-IR
SHIFT-DR
EXIT1-DR
EXIT1-IR
PAUSE-DR
PAUSE-IR
EXIT2-IR
EXIT2-DR
UPDATE-DR
UPDATE-IR
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 49-4. IEEE 1149.1-2001 TAP controller finite state machine
49.4.3.1 Enabling the TAP controller
The JTAGC TAP controller is enabled by setting the JTAGC enable to a logic 1 value.
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1222 Freescale Semiconductor, Inc.