Information

Signal multiplexing

access

Peripheral

bridge

Module signals

I S

Figure 3-51. I

S configuration

Table 3-62. Reference links to related information

Topic Related module Reference

Full description I

S I2S

System memory map System memory map

Clocking Clock Distribution

Power management Power management

Signal multiplexing Port control Signal Multiplexing

3.9.5.1 Instantiation information

This device contains one I

S module.

As configured on the device, module features include:

• TX data lines: 1

• RX data lines: 1

• FIFO size (words): 4

• Maximum words per frame: 16

• Maximum bit clock divider: 512

3.9.5.2 I

S/SAI clocking

3.9.5.2.1 Audio Master Clock

The audio master clock (MCLK) is used to generate the bit clock when the receiver or

transmitter is configured for an internally generated bit clock. The audio master clock can

also be output to or input from a pin. The transmitter and receiver have the same audio

master clock inputs.

Communication interfaces

K20 Sub-Family Reference Manual, Rev. 2, Feb 2012

124 Freescale Semiconductor, Inc.