Information

In Stop mode, if the Transmitter Stop Enable (TCSR[STOPE]) bit is clear, the transmitter

is disabled after completing the current transmit frame, and, if the Receiver Stop Enable

(RCSR[STOPE]) bit is clear, the receiver is disabled after completing the current receive

frame. Entry into Stop mode is prevented–not acknowledged–while waiting for the

transmitter and receiver to be disabled at the end of the current frame.

3.9.5.3.2 Low-leakage modes

When entering low-leakage modes, the Stop Enable (TCSR[STOPE] and

RCSR[STOPE]) bits are ignored and the SAI is disabled after completing the current

transmit and receive Frames. Entry into stop mode is prevented (not acknowledged)

while waiting for the transmitter and receiver to be disabled at the end of the current

frame.

Human-machine interfaces (HMI)

3.10.1 GPIO configuration

This section summarizes how the module has been configured in the chip. For a

comprehensive description of the module itself, see the module’s dedicated chapter.

Signal multiplexing

access

Peripheral

bridge

Module signals

GPIO controller

Crossbar switch

Transfers

Figure 3-52. GPIO configuration

Table 3-65. Reference links to related information

Topic Related module Reference

Full description GPIO GPIO

System memory map System memory map

Clocking Clock Distribution

Power management Power management

Table continues on the next page...

3.10

Chapter 3 Chip Configuration

K20 Sub-Family Reference Manual, Rev. 2, Feb 2012

Freescale Semiconductor, Inc. 127