Information

Table 4-1. System memory map (continued)
System 32-bit Address Range Destination Slave Access
0x2010_0000–0x21FF_FFFF Reserved –
0x2200_0000–0x23FF_FFFF Aliased to SRAM_U bitband Cortex-M4 core
only
0x2400_0000–0x3FFF_FFFF Reserved –
0x4000_0000–0x4007_FFFF Bitband region for AIPS Cortex-M4 core &
DMA/EzPort
0x4008_0000–0x400F_EFFF Reserved –
0x400F_F000–0x400F_FFFF Bitband region for general purpose input/output (GPIO) Cortex-M4 core &
DMA/EzPort
0x4010_0000–0x41FF_FFFF Reserved –
0x4200_0000–0x43FF_FFFF Aliased to AIPS and GPIO bitband Cortex-M4 core
only
0x4400_0000–0xDFFF_FFFF Reserved –
0xE000_0000–0xE00F_FFFF Private Peripherals Cortex-M4 core
only
0xE010_0000–0xFFFF_FFFF Reserved –
NOTE
1. EzPort master port is statically muxed with DMA master
port. Access rights to AIPS-Lite peripheral bridge and
general purpose input/output (GPIO) module address space
is limited to the core, DMA, and EzPort.
2. ARM Cortex-M4 core access privileges also includes
accesses via the debug interface.
4.2.1 Aliased bit-band regions
The SRAM_U, AIPS-Lite, and general purpose input/output (GPIO) module resources
reside in the Cortex-M4 processor bit-band regions.
The processor also includes two 32 MB aliased bit-band regions associated with the two
1 MB bit-band spaces. Each 32-bit location in the 32 MB space maps to an individual bit
in the bit-band region. A 32-bit write in the alias region has the same effect as a read-
modify-write operation on the targeted bit in the bit-band region.
Bit 0 of the value written to the alias region determines what value is written to the target
bit:
• Writing a value with bit 0 set writes a 1 to the target bit.
• Writing a value with bit 0 clear writes a 0 to the target bit.
System memory map
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
132 Freescale Semiconductor, Inc.