Information

4.5 Peripheral bridge (AIPS-Lite) memory map

The peripheral memory map is accessible via one slave port on the crossbar in the

0x4000_0000–0x4007_FFFF region. The device implements one peripheral bridge that

defines a 512 KB address space.

Modules that are disabled via their clock gate control bits in the SIM registers disable the

associated AIPS slots. Access to any address within an unimplemented or disabled

peripheral bridge slot results in a transfer error termination.

For programming model accesses via the peripheral bridges, there is generally only a

small range within the 4 KB slots that is implemented. Accessing an address that is not

implemented in the peripheral results in a transfer error termination.

4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map

Table 4-2. Peripheral bridge 0 slot assignments

System 32-bit base address Slot

number

Module

0x4000_0000 0 Peripheral bridge 0 (AIPS-Lite 0)

0x4000_1000 1 —

0x4000_2000 2 —

0x4000_3000 3 —

0x4000_4000 4 Crossbar switch

0x4000_5000 5 —

0x4000_6000 6 —

0x4000_7000 7 —

0x4000_8000 8 DMA controller

0x4000_9000 9 DMA controller transfer control descriptors

0x4000_A000 10 —

0x4000_B000 11 —

0x4000_C000 12 —

0x4000_D000 13 —

0x4000_E000 14 —

0x4000_F000 15 —

0x4001_0000 16 —

0x4001_1000 17 —

Table continues on the next page...

Chapter 4 Memory Map

K20 Sub-Family Reference Manual, Rev. 2, Feb 2012

Freescale Semiconductor, Inc. 135