Information

Table 5-1. Clock Summary (continued)
Clock name Run mode
clock frequency
VLPR mode
clock frequency
Clock source Clock is disabled
when…
Flash clock Up to 25 MHz Up to 1 MHz MCGOUTCLK clock
divider
In all stop modes
Internal reference
(MCGIRCLK)
30-40 kHz or 4 MHz 4 MHz only MCG MCG_C1[IRCLKEN]
cleared,
Stop mode and
MCG_C1[IREFSTEN]
cleared, or
VLPS/LLS/VLLS mode
External reference
(OSCERCLK)
Up to 50 MHz
(bypass),
30-40 kHz, or
3-32 MHz (crystal)
Up to 16 MHz
(bypass),
30-40 kHz (low-range
crystal) or
Up to 16 MHz (high-
range crystal)
System OSC System OSC's
OSC_CR[ERCLKEN]
cleared, or
Stop mode and
OSC_CR[EREFSTEN]
cleared
External reference
32kHz
(ERCLK32K)
30-40 kHz 30-40 kHz System OSC or RTC
OSC depending on
SIM_SOPT1[OSC32K
SEL]
System OSC's
OSC_CR[ERCLKEN]
cleared or
RTC's RTC_CR[OSCE]
cleared
RTC_CLKOUT 1 Hz or 32 kHz 1 Hz or 32 kHz RTC clock Clock is disabled in
LLS and VLLSx modes
LPO 1 kHz 1 kHz PMC in VLLS0
USB FS clock 48 MHz N/A MCGPLLCLK or
MCGFLLCLK with
fractional clock divider,
or
USB_CLKIN
USB FS OTG is
disabled
I2S master clock Up to 25 MHz Up to 12.5 MHz System clock,
MCGPLLCLK,
OSCERCLK with
fractional clock divider,
or
I2S_CLKIN
I
2
S is disabled
TRACE clock Up to 50 MHz Up to 4 MHz System clock or
MCGOUTCLK
Trace is disabled
5.5 Internal clocking requirements
The clock dividers are programmed via the SIM module’s CLKDIV registers. Each
divider is programmable from a divide-by-1 through divide-by-16 setting. The following
requirements must be met when configuring the clocks for this device:
Internal clocking requirements
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
144 Freescale Semiconductor, Inc.