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1. The core and system clock frequencies must be 50 MHz or slower.
2. The bus clock frequency must be programmed to 50 MHz or less and an integer
divide of the core clock.
3. The flash clock frequency must be programmed to 25 MHz or less, less than or equal
to the bus clock, and an integer divide of the core clock.
The following are a few of the more common clock configurations for this device:
Option 1:
Clock Frequency
Core clock 50 MHz
System clock 50 MHz
Bus clock 50 MHz
Flash clock 25 MHz
5.5.1 Clock divider values after reset
Each clock divider is programmed via the SIM module’s CLKDIVn registers. The flash
memory's FTFL_FOPT[LPBOOT] bit controls the reset value of the core clock, system
clock, bus clock, and flash clock dividers as shown below:
FTFL_FOPT
[LPBOOT]
Core/system clock Bus clock Flash clock Description
0 0x7 (divide by 8) 0x7 (divide by 8) 0xF (divide by 16) Low power boot
1 0x0 (divide by 1) 0x0 (divide by 1) 0x1 (divide by 2) Fast clock boot
This gives the user flexibility for a lower frequency, low-power boot option. The flash
erased state defaults to fast clocking mode, since where the low power boot
(FTFL_FOPT[LPBOOT]) bit resides in flash is logic 1 in the flash erased state.
To enable the low power boot option program FTFL_FOPT[LPBOOT] to zero. During
the reset sequence, if LPBOOT is cleared, the system is in a slow clock configuration.
Upon any system reset, the clock dividers return to this configurable reset state.
5.5.2 VLPR mode clocking
The clock dividers cannot be changed while in VLPR mode. They must be programmed
prior to entering VLPR mode to guarantee:
• the core/system and bus clocks are less than or equal to 4 MHz, and
• the flash memory clock is less than or equal to 1 MHz
Chapter 5 Clock Distribution
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 145