Information

Note that the nTRST signal is initially configured as disabled, however once configured
to its JTAG functionality its associated input pin is configured as:
• nTRST in PU
6.2.2.1 External pin reset (PIN)
On this device, RESET is a dedicated pin. This pin is open drain and has an internal
pullup device. Asserting RESET wakes the device from any mode. During a pin reset, the
RCM's SRS0[PIN] bit is set.
6.2.2.1.1 Reset pin filter
The RESET pin filter supports filtering from both the 1 kHz LPO clock and the bus
clock. A separate filter is implemented for each clock source. In stop and VLPS mode
operation, this logic either switches to bypass operation or has continued filtering
operation depending on the filtering mode selected. In low leakage stop modes, a separate
LPO filter in the LLWU can continue filtering the RESET pin.
The RPFC[RSTFLTSS], RPFC[RSTFLTSRW], and RPFW[RSTFLTSEL] fields in the
reset control (RCM) register set control this functionality; see the RCM chapter. The
filters are asynchronously reset by Chip POR. The reset value for each filter assumes the
RESET pin is negated.
The two clock options for the
RESET pin filter when the chip is not in low leakage
modes are the LPO (1 kHz) and bus clock. For low leakage modes VLLS3, VLLS2,
VLLS1, the LLWU provides control (in the LLWU_RST register) of an optional fixed
digital filter running the LPO. When entering VLLS0, the RESET pin filter is disabled
and bypassed.
The LPO filter has a fixed filter value of 3. Due to a synchronizer on the input data, there
is also some associated latency (2 cycles). As a result, 5 cycles are required to complete a
transition from low to high or high to low.
The bus filter initializes to off (logic 1) when the bus filter is not enabled. The bus clock
is used when the filter selects bus clock, and the number of counts is controlled by the
RCM's RPFW[RSTFLTSEL] field.
Chapter 6 Reset and Boot
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 155