Information

6.2.5.3 Resetting the Debug subsystem
Use the CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register to reset the debug
modules. However, as explained below, using the CDBGRSTREQ bit does not reset all
debug-related registers.
CDBGRSTREQ resets the debug-related registers within the following modules:
• SWJ-DP
• AHB-AP
• TPIU
• MDM-AP (MDM control and status registers)
CDBGRSTREQ does not reset the debug-related registers within the following modules:
• CM4 core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR)
• FPB
• DWT
• ITM
• NVIC
• Crossbar bus switch
1
• AHB-AP
1
• Private peripheral bus
1
6.3 Boot
This section describes the boot sequence, including sources and options.
6.3.1 Boot sources
This device only supports booting from internal flash. Any secondary boot must go
through an initialization sequence in flash.
6.3.2 Boot options
The device's functional mode is controlled by the state of the EzPort chip select
(EZP_CS) pin during reset.
1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available
during System Reset.
Chapter 6 Reset and Boot
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 161