Information

7. When the system exits reset, the processor sets up the stack, program counter (PC),
and link register (LR). The processor reads the start SP (SP_main) from vector-table
offset 0. The core reads the start PC from vector-table offset 4. LR is set to
0xFFFF_FFFF. The CPU begins execution at the PC location. EzPort mode is
entered instead of the normal CPU execution if Ezport mode was latched during the
sequence.
8. If FlexNVM is enabled, the flash controller continues to restore the FlexNVM data.
This data is not available immediately out of reset and the system should not access
this data until the flash controller completes this initialization step as indicated by the
EEERDY flag.
Subsequent system resets follow this reset flow beginning with the step where system
clocks are enabled.
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K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
164 Freescale Semiconductor, Inc.