Information

If the oscillator was configured to continue running during VLLSx modes, it must be re-
configured before the ACKISO bit is cleared. The oscillator configuration within the
MCG is cleared after VLLSx recovery and the oscillator will stop when ACKISO is
cleared unless the register is re-configured.
7.4 Power mode transitions
The following figure shows the power mode transitions. Any reset always brings the chip
back to the normal run state. In run, wait, and stop modes active power regulation is
enabled. The VLPx modes are limited in frequency, but offer a lower power operating
mode than normal modes. The LLS and VLLSx modes are the lowest power stop modes
based on amount of logic or memory that is required to be retained by the application.
Power mode transitions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
168 Freescale Semiconductor, Inc.