Information

Table 7-2. Module operation in low power modes (continued)
Modules Stop VLPR VLPW VLPS LLS VLLSx
Mode Controller FF FF FF FF FF FF
LLWU
1
static static static static FF FF
2
Regulator ON low power low power low power low power low power in
VLLS2/3, OFF
in VLLS0/1
LVD ON disabled disabled disabled disabled disabled
Brown-out
Detection
ON ON ON ON ON ON in
VLLS1/2/3,
optionally
disabled in
VLLS0
3
DMA static FF FF static static OFF
Watchdog FF FF FF FF static OFF
EWM static FF static static static OFF
Clocks
1kHz LPO ON ON ON ON ON ON in
VLLS1/2/3, OFF
in VLLS0
System
oscillator (OSC)
OSCERCLK
optional
OSCERCLK
max of 4MHz
crystal
OSCERCLK
max of 4MHz
crystal
OSCERCLK
max of 4MHz
crystal
limited to low
range/low
power
limited to low
range/low
power in
VLLS1/2/3, OFF
in VLLS0
MCG static -
MCGIRCLK
optional; PLL
optionally on
but gated
4 MHz IRC 4 MHz IRC static - no clock
output
static - no clock
output
OFF
Core clock OFF 4 MHz max OFF OFF OFF OFF
System clock OFF 4 MHz max 4 MHz max OFF OFF OFF
Bus clock OFF 4 MHz max 4 MHz max OFF OFF OFF
Memory and memory interfaces
Flash powered 1 MHz max
access - no
pgm
low power low power OFF OFF
Portion of
SRAM_U
4
low power low power low power low power low power low power in
VLLS3,2
Remaining
SRAM_U and
all of SRAM_L
low power low power low power low power low power low power in
VLLS3
FlexMemory low power low power
5
low power low power low power OFF
Register files
6
powered powered powered powered powered powered
EzPort disabled disabled disabled disabled disabled disabled
Table continues on the next page...
Chapter 7 Power Management
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 171