Information

Private Peripheral Bus
(internal)
Trigger
ITM
TPIU
Core
FPB
AHB-AP
NVIC
SWJ-DP
Bus
Matrix
APB
i/f
Trace port
(serial wire
or multi-pin)
Cortex-M4
SW/
JTAG
Debug
Sleep
Interrupts
INTNMI
SLEEPING
SLEEPDEEP
INTISR[239:0]
AWIC
DWT
ROM
Table
ETM
Instr. Data
MCM
I-code bus
D-code bus
System bus
Code bus
MDM-AP
Figure 9-1. Cortex-M4 Debug Topology
The following table presents a brief description of each one of the debug components.
Table 9-1. Debug Components Description
Module Description
SWJ-DP+ cJTAG Modified Debug Port with support for SWD, JTAG, cJTAG
AHB-AP AHB Master Interface from JTAG to debug module and SOC
system memory maps
JTAG-AP Bridge to DFT/BIST resources.
ROM Table Identifies which debug IP is available.
Core Debug Singlestep, Register Access, Run, Core Status
ITM S/W Instrumentation Messaging + Simple Data Trace
Messaging + Watchpoint Messaging
DWT (Data and Address Watchpoints) 4 data and address watchpoints (configurable for less, but 4
seems to be accepted)
Table continues on the next page...
Introduction
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
178 Freescale Semiconductor, Inc.