Information
Section Number Title Page
23.7.12 Watchdog Prescaler register (WDOG_PRESC)..........................................................................................424
23.8 Watchdog operation with 8-bit access..........................................................................................................................424
23.8.1 General guideline.........................................................................................................................................425
23.8.2 Refresh and unlock operations with 8-bit access.........................................................................................425
23.9 Restrictions on watchdog operation..............................................................................................................................426
Chapter 24
Multipurpose Clock Generator (MCG)
24.1 Introduction...................................................................................................................................................................429
24.1.1 Features........................................................................................................................................................429
24.1.2 Modes of Operation.....................................................................................................................................432
24.2 External Signal Description..........................................................................................................................................433
24.3 Memory Map/Register Definition.................................................................................................................................433
24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................434
24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................435
24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................436
24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................437
24.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................438
24.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................439
24.3.7 MCG Status Register (MCG_S)..................................................................................................................441
24.3.8 MCG Status and Control Register (MCG_SC)............................................................................................442
24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................444
24.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................444
24.3.11 MCG Control 7 Register (MCG_C7)...........................................................................................................444
24.3.12 MCG Control 8 Register (MCG_C8)...........................................................................................................445
24.4 Functional Description..................................................................................................................................................446
24.4.1 MCG mode state diagram............................................................................................................................446
24.4.2 Low Power Bit Usage..................................................................................................................................451
24.4.3 MCG Internal Reference Clocks..................................................................................................................451
24.4.4 External Reference Clock............................................................................................................................452
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
18 Freescale Semiconductor, Inc.