Information

Table 9-5. MDM-AP Control register assignments (continued)
Bit Name Secure
1
Description
7 LLS, VLLSx Status Acknowledge N Set this bit to acknowledge the DAP LLS and VLLS Status bits have
been read. This acknowledge automatically clears the status bits.
This bit is used by the debugger to clear the sticky LLS and VLLSx
mode entry status bits. This bit is asserted and cleared by the
debugger.
8 Timestamp Disable N Set this bit to disable the 48-bit global trace timestamp counter during
debug halt mode when the core is halted.
0 The timestamp counter continues to count assuming trace is
enabled and the ETM is enabled. (default)
1 The timestamp counter freezes when the core has halted (debug
halt mode).
9 –
31
Reserved for future use N
1. Command available in secure mode
9.5.2 MDM-AP Status Register
Table 9-6. MDM-AP Status register assignments
Bit Name Description
0 Flash Mass Erase Acknowledge The Flash Mass Erase Acknowledge bit is cleared after any system reset.
The bit is also cleared at launch of a mass erase command due to write of
Flash Mass Erase in Progress bit in MDM AP Control Register. The Flash
Mass Erase Acknowledge is set after Flash control logic has started the
mass erase operation.
When mass erase is disabled (via MEEN and SEC settings), an erase
request due to seting of Flash Mass Erase in Progress bit is not
acknowledged.
1 Flash Ready Indicate Flash has been initialized and debugger can be configured even
if system is continuing to be held in reset via the debugger.
2 System Security Indicates the security state. When secure, the debugger does not have
access to the system bus or any memory mapped peripherals. This bit
indicates when the part is locked and no system bus access is possible.
3 System Reset Indicates the system reset state.
0 System is in reset
1 System is not in reset
4 Reserved
5 Mass Erase Enable Indicates if the MCU can be mass erased or not
0 Mass erase is disabled
1 Mass erase is enabled
Table continues on the next page...
Chapter 9 Debug
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 185