Information

Table 10-1. Reference links to related information (continued)
Topic Related module Reference
Clocking Clock Distribution
Register access Peripheral bus
controller
Peripheral bridge
10.2.1 Port control and interrupt module features
• Five 32-pin ports
NOTE
Not all pins are available on the device. See the following
section for details.
NOTE
The digital filters are only available on Port D.
• Each 32-pin port is assigned one interrupt.
• The digital filter option has two clock source options: bus clock and 1-kHz LPO. The
1-kHz LPO option gives users this feature in low power modes.
• The digital filter is configurable from 1 to 32 clock cycles when enabled.
10.2.2 PCRn reset values for port A
PCRn bit reset values for port A are 1 for the following bits:
• For PCR0: bits 1, 6, 8, 9, and 10.
• For PCR1 to PCR4: bits 0, 1, 6, 8, 9, and 10.
• For PCR5 : bits 0, 1, and 6.
All other PCRn bit reset values for port A are 0.
10.2.3 Clock gating
The clock to the port control module can be gated on and off using the SCGC5[PORTx]
bits in the SIM module. These bits are cleared after any reset, which disables the clock to
the corresponding module to conserve power. Prior to initializing the corresponding
module, set SCGC5[PORTx] in the SIM module to enable the clock. Before turning off
the clock, make sure to disable the module. For more details, refer to the clock
distribution chapter.
Signal Multiplexing Integration
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
192 Freescale Semiconductor, Inc.