Information

64
MAP
BGA
64
LQF
P
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
H2 18 — CMP1_IN3/
ADC0_SE2
3
CMP1_IN3/
ADC0_SE2
3
CMP1_IN3/
ADC0_SE2
3
H3 19 9 XTAL32 XTAL32 XTAL32
H4 20 10 EXTAL32 EXTAL32 EXTAL32
H5 21 11 VBAT VBAT VBAT
D3 22 12 PTA0 JTAG_TCL
K/
SWD_CLK/
EZP_CLK
TSI0_CH1 PTA0 UART0_CT
S_b/
UART0_CO
L_b
FTM0_CH5 JTAG_TCL
K/
SWD_CLK
EZP_CLK
D4 23 13 PTA1 JTAG_TDI/
EZP_DI
TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI
E5 24 14 PTA2 JTAG_TDO
/
TRACE_S
WO/
EZP_DO
TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO
/
TRACE_S
WO
EZP_DO
D5 25 15 PTA3 JTAG_TMS
/SWD_DIO
TSI0_CH4 PTA3 UART0_RT
S_b
FTM0_CH0 JTAG_TMS
/SWD_DIO
G5 26 16 PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5 PTA4/
LLWU_P3
FTM0_CH1 NMI_b EZP_CS_b
F5 27 — PTA5 DISABLED PTA5 USB_CLKI
N
FTM0_CH2 I2S0_TX_B
CLK
JTAG_TRS
T_b
H6 28 — PTA12 DISABLED PTA12 FTM1_CH0 I2S0_TXD0 FTM1_QD_
PHA
G6 29 — PTA13/
LLWU_P4
DISABLED PTA13/
LLWU_P4
FTM1_CH1 I2S0_TX_F
S
FTM1_QD_
PHB
G7 30 — VDD VDD VDD
H7 31 — VSS VSS VSS
H8 32 17 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT
2
FTM_CLKI
N0
G8 33 18 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT
0
FTM_CLKI
N1
LPTMR0_A
LT1
F8 34 19 RESET_b RESET_b RESET_b
F7 35 20 PTB0/
LLWU_P5
ADC0_SE8
/TSI0_CH0
ADC0_SE8
/TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL FTM1_CH0 FTM1_QD_
PHA
F6 36 21 PTB1 ADC0_SE9
/TSI0_CH6
ADC0_SE9
/TSI0_CH6
PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_
PHB
E7 37 — PTB2 ADC0_SE1
2/
TSI0_CH7
ADC0_SE1
2/
TSI0_CH7
PTB2 I2C0_SCL UART0_RT
S_b
FTM0_FLT
3
E8 38 — PTB3 ADC0_SE1
3/
TSI0_CH8
ADC0_SE1
3/
TSI0_CH8
PTB3 I2C0_SDA UART0_CT
S_b/
UART0_CO
L_b
FTM0_FLT
0
E6 39 — PTB16 TSI0_CH9 TSI0_CH9 PTB16 UART0_RX EWM_IN
D7 40 — PTB17 TSI0_CH10 TSI0_CH10 PTB17 UART0_TX EWM_OUT
_b
Pinout
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
194 Freescale Semiconductor, Inc.