Information

64
MAP
BGA
64
LQF
P
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
D6 41 — PTB18 TSI0_CH11 TSI0_CH11 PTB18 I2S0_TX_B
CLK
C7 42 — PTB19 TSI0_CH12 TSI0_CH12 PTB19 I2S0_TX_F
S
D8 43 — PTC0 ADC0_SE1
4/
TSI0_CH13
ADC0_SE1
4/
TSI0_CH13
PTC0 SPI0_PCS4 PDB0_EXT
RG
C6 44 22 PTC1/
LLWU_P6
ADC0_SE1
5/
TSI0_CH14
ADC0_SE1
5/
TSI0_CH14
PTC1/
LLWU_P6
SPI0_PCS3 UART1_RT
S_b
FTM0_CH0 I2S0_TXD0
B7 45 23 PTC2 ADC0_SE4
b/
CMP1_IN0/
TSI0_CH15
ADC0_SE4
b/
CMP1_IN0/
TSI0_CH15
PTC2 SPI0_PCS2 UART1_CT
S_b
FTM0_CH1 I2S0_TX_F
S
C8 46 24 PTC3/
LLWU_P7
CMP1_IN1 CMP1_IN1 PTC3/
LLWU_P7
SPI0_PCS1 UART1_RX FTM0_CH2 I2S0_TX_B
CLK
E3 47 — VSS VSS VSS
E4 48 — VDD VDD VDD
B8 49 25 PTC4/
LLWU_P8
DISABLED PTC4/
LLWU_P8
SPI0_PCS0 UART1_TX FTM0_CH3 CMP1_OU
T
A8 50 26 PTC5/
LLWU_P9
DISABLED PTC5/
LLWU_P9
SPI0_SCK LPTMR0_A
LT2
I2S0_RXD0 CMP0_OU
T
A7 51 27 PTC6/
LLWU_P10
CMP0_IN0 CMP0_IN0 PTC6/
LLWU_P10
SPI0_SOU
T
PDB0_EXT
RG
I2S0_RX_B
CLK
I2S0_MCL
K
B6 52 28 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_SOF_
OUT
I2S0_RX_F
S
A6 53 — PTC8 CMP0_IN2 CMP0_IN2 PTC8 I2S0_MCL
K
B5 54 — PTC9 CMP0_IN3 CMP0_IN3 PTC9 I2S0_RX_B
CLK
B4 55 — PTC10 DISABLED PTC10 I2S0_RX_F
S
A5 56 — PTC11/
LLWU_P11
DISABLED PTC11/
LLWU_P11
C3 57 — PTD0/
LLWU_P12
DISABLED PTD0/
LLWU_P12
SPI0_PCS0 UART2_RT
S_b
A4 58 — PTD1 ADC0_SE5
b
ADC0_SE5
b
PTD1 SPI0_SCK UART2_CT
S_b
C2 59 — PTD2/
LLWU_P13
DISABLED PTD2/
LLWU_P13
SPI0_SOU
T
UART2_RX
B3 60 — PTD3 DISABLED PTD3 SPI0_SIN UART2_TX
A3 61 29 PTD4/
LLWU_P14
DISABLED PTD4/
LLWU_P14
SPI0_PCS1 UART0_RT
S_b
FTM0_CH4 EWM_IN
C1 62 30 PTD5 ADC0_SE6
b
ADC0_SE6
b
PTD5 SPI0_PCS2 UART0_CT
S_b/
UART0_CO
L_b
FTM0_CH5 EWM_OUT
_b
Chapter 10 Signal Multiplexing and Signal Descriptions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 195