Information

1
A PTE0
B
PTE1/
LLWU_P0
C PTD5
D USB0_DM
E USB0_DP
F ADC0_DM0
G ADC0_DP0
1
H
VREF_OUT/
CMP1_IN5/
CMP0_IN5
2
PTD7
PTD6/
LLWU_P15
PTD2/
LLWU_P13
VREGIN
VOUT33
ADC0_DM3
ADC0_DP3
2
CMP1_IN3/
ADC0_SE23
3
PTD4/
LLWU_P14
PTD3
PTD0/
LLWU_P12
PTA0
VSS
VSSA
VREFL
3
XTAL32
4
PTD1
PTC10
VSS
PTA1
VDD
VDDA
VREFH
4
EXTAL32
5
PTC11/
LLWU_P11
PTC9
VDD
PTA3
PTA2
PTA5
PTA4/
LLWU_P3
5
VBAT
6
PTC8
PTC7
PTC1/
LLWU_P6
PTB18
PTB16
PTB1
PTA13/
LLWU_P4
6
PTA12
7
PTC6/
LLWU_P10
PTC2
PTB19
PTB17
PTB2
PTB0/
LLWU_P5
VDD
7
VSS
8
A
PTC5/
LLWU_P9
B
PTC4/
LLWU_P8
C
PTC3/
LLWU_P7
D
PTC0
EPTB3
FRESET_b
GPTA19
8
HPTA18
Figure 10-3. K20 64 MAPBGA Pinout Diagram
10.4 Module Signal Description Tables
The following sections correlate the chip-level signal name with the signal name used in
the module's chapter. They also briefly describe the signal function and direction.
10.4.1 Core Modules
Table 10-2. JTAG Signal Descriptions
Chip signal name Module signal
name
Description I/O
JTAG_TMS JTAG_TMS/
SWD_DIO
JTAG Test Mode Selection I/O
JTAG_TCLK JTAG_TCLK/
SWD_CLK
JTAG Test Clock I
JTAG_TDI JTAG_TDI JTAG Test Data Input I
JTAG_TDO JTAG_TDO/
TRACE_SWO
JTAG Test Data Output O
JTAG_TRST JTAG_TRST_b JTAG Reset I
Module Signal Description Tables
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
198 Freescale Semiconductor, Inc.