Information

Table 10-11. CMP 0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
CMP0_IN[5:0] IN[5:0] Analog voltage inputs I
CMP0_OUT CMPO Comparator output O
Table 10-12. CMP 1 Signal Descriptions
Chip signal name Module signal
name
Description I/O
CMP1_IN[5:0] IN[5:0] Analog voltage inputs I
CMP1_OUT CMPO Comparator output O
Table 10-13. VREF Signal Descriptions
Chip signal name Module signal
name
Description I/O
VREF_OUT VREF_OUT Internally-generated Voltage Reference output O
10.4.6 Communication Interfaces
Table 10-14. USB FS OTG Signal Descriptions
Chip signal name Module signal
name
Description I/O
USB0_DM usb_dm USB D- analog data signal on the USB bus. I/O
USB0_DP usb_dp USB D+ analog data signal on the USB bus. I/O
USB_CLKIN — Alternate USB clock input I
Table 10-15. USB VREG Signal Descriptions
Chip signal name Module signal
name
Description I/O
VOUT33 reg33_out Regulator output voltage O
VREGIN reg33_in Unregulated power supply I
Table 10-16. SPI 0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
SPI0_PCS0 PCS0/SS Master mode: Peripheral Chip Select 0 output
Slave mode: Slave Select input
I/O
Table continues on the next page...
Chapter 10 Signal Multiplexing and Signal Descriptions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 201