Information

Table 10-16. SPI 0 Signal Descriptions (continued)
Chip signal name Module signal
name
Description I/O
SPI0_PCS[3:1] PCS[3:1] Master mode: Peripheral Chip Select 1 – 3
Slave mode: Unused
O
SPI0_PCS4 PCS4 Master mode: Peripheral Chip Select 4
Slave mode: Unused
O
SPI0_SIN SIN Serial Data In I
SPI0_SOUT SOUT Serial Data Out O
SPI0_SCK SCK Master mode: Serial Clock (output)
Slave mode: Serial Clock (input)
I/O
Table 10-17. I
2
C 0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
I2C0_SCL SCL Bidirectional serial clock line of the I
2
C system. I/O
I2C0_SDA SDA Bidirectional serial data line of the I
2
C system. I/O
Table 10-18. UART 0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
UART0_CTS CTS Clear to send I
UART0_RTS RTS Request to send O
UART0_TX TXD Transmit data O
UART0_RX RXD Receive data I
UART0_COL Collision Collision detect I
Table 10-19. UART 1 Signal Descriptions
Chip signal name Module signal
name
Description I/O
UART1_CTS CTS Clear to send I
UART1_RTS RTS Request to send O
UART1_TX TXD Transmit data O
UART1_RX RXD Receive data I
Table 10-20. UART 2 Signal Descriptions
Chip signal name Module signal
name
Description I/O
UART2_CTS CTS Clear to send I
Table continues on the next page...
Module Signal Description Tables
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
202 Freescale Semiconductor, Inc.