Information

Table 11-1. Signal properties
Name Function I/O Reset Pull
PORTx[31:0] External interrupt I/O 0 -
NOTE
Not all pins within each port are implemented on each device.
11.3 Detailed signal description
The following table contains the detailed signal description for the PORT interface.
Table 11-2. PORT interface—detailed signal description
Signal I/O Description
PORTx[31:0] I/O External interrupt.
State meaning Asserted—pin is logic one.
Negated—pin is logic zero.
Timing Assertion—may occur at any time and can assert
asynchronously to the system clock.
Negation—may occur at any time and can assert
asynchronously to the system clock.
11.4 Memory map and register definition
Any read or write access to the PORT memory space that is outside the valid memory
map results in a bus error. All register accesses complete with zero wait states.
PORT memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4004_9000 Pin Control Register n (PORTA_PCR0) 32 R/W See section 11.4.1/213
4004_9004 Pin Control Register n (PORTA_PCR1) 32 R/W See section 11.4.1/213
4004_9008 Pin Control Register n (PORTA_PCR2) 32 R/W See section 11.4.1/213
4004_900C Pin Control Register n (PORTA_PCR3) 32 R/W See section 11.4.1/213
4004_9010 Pin Control Register n (PORTA_PCR4) 32 R/W See section 11.4.1/213
4004_9014 Pin Control Register n (PORTA_PCR5) 32 R/W See section 11.4.1/213
Table continues on the next page...
Chapter 11 Port control and interrupts (PORT)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 207