Information

PORTx_PCRn field descriptions (continued)
Field Description
24
ISF
Interrupt Status Flag
The pin interrupt configuration is valid in all digital pin muxing modes.
0 Configured interrupt is not detected.
1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the
corresponding flag will be cleared automatically at the completion of the requested DMA transfer.
Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level
sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is
cleared.
23–20
Reserved
This read-only field is reserved and always has the value zero.
19–16
IRQC
Interrupt Configuration
The pin interrupt configuration is valid in all digital pin muxing modes. The corresponding pin is configured
to generate interrupt/DMA request as follows:
0000 Interrupt/DMA request disabled.
0001 DMA request on rising edge.
0010 DMA request on falling edge.
0011 DMA request on either edge.
0100 Reserved.
1000 Interrupt when logic zero.
1001 Interrupt on rising edge.
1010 Interrupt on falling edge.
1011 Interrupt on either edge.
1100 Interrupt when logic one.
Others Reserved.
15
LK
Lock Register
0 Pin Control Register fields [15:0] are not locked.
1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
14–11
Reserved
This read-only field is reserved and always has the value zero.
10–8
MUX
Pin Mux Control
Not all pins support all pin muxing slots. Unimplemented pin muxing slots are reserved and may result in
configuring the pin for a different pin muxing slot.
The corresponding pin is configured in the following pin muxing slot as follows:
000 Pin disabled (analog).
001 Alternative 1 (GPIO).
010 Alternative 2 (chip-specific).
011 Alternative 3 (chip-specific).
100 Alternative 4 (chip-specific).
101 Alternative 5 (chip-specific).
110 Alternative 6 (chip-specific).
111 Alternative 7 (chip-specific).
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
214 Freescale Semiconductor, Inc.