Information

11.5 Functional description
11.5.1 Pin control
Each port pin has a corresponding pin control register, PORT_PCRn, associated with it.
The upper half of the pin control register configures the pin's capability to either interrupt
the CPU or request a DMA transfer, on a rising/falling edge or both edges as well as a
logic level occurring on the port pin. It also includes a flag to indicate that an interrupt
has occurred.
The lower half of the pin control register configures the following functions for each pin
within the 32-bit port.
• Pullup or pulldown enable
• Drive strength and slew rate configuration
• Open drain enable
• Passive input filter enable
• Pin Muxing mode
The functions apply across all digital Pin Muxing modes and individual peripherals do
not override the configuration in the pin control register. For example, if an I
2
C function
is enabled on a pin, that does not override the pullup or open drain configuration for that
pin.
When the Pin Muxing mode is configured for analog or is disabled, all the digital
functions on that pin are disabled. This includes the pullup and pulldown enables, digital
output buffer enable, digital input buffer enable, and passive filter enable.
A lock field also exists that allows the configuration for each pin to be locked until the
next system reset. When locked, writes to the lower half of that pin control register are
ignored, although a bus error is not generated on an attempted write to a locked register.
The configuration of each pin control register is retained when the PORT module is
disabled.
11.5.2 Global pin control
The two global pin control registers allow a single register write to update the lower half
of the pin control register on up to sixteen pins, all with the same value. Registers that are
locked cannot be written using the global pin control registers.
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
218 Freescale Semiconductor, Inc.