Information

12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)
Address: SIM_SCGC5 is 4004_7000h base + 1038h offset = 4004_8038h
Bit 31 30 29 28 27 26 25 24
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
23 22 21 20 19 18 17 16
R
0 1 0
W
Reset
0 0 0 0 0 1 0 0
Bit
15 14 13 12 11 10 9 8
R
0
PORTE PORTD PORTC PORTB PORTA
1
W
Reset
0 0 0 0 0 0 0 1
Bit
7 6 5 4 3 2 1 0
R
1 0
TSI
0 0 1
LPTIMER
W
Reset
1 0 0 0 0 0 1 0
SIM_SCGC5 field descriptions
Field Description
31–19
Reserved
This read-only field is reserved and always has the value zero.
18
Reserved
This read-only field is reserved and always has the value one.
17–14
Reserved
This read-only field is reserved and always has the value zero.
13
PORTE
Port E Clock Gate Control
This bit controls the clock gate to the Port E module.
0 Clock disabled
1 Clock enabled
12
PORTD
Port D Clock Gate Control
This bit controls the clock gate to the Port D module.
0 Clock disabled
1 Clock enabled
11
PORTC
Port C Clock Gate Control
This bit controls the clock gate to the Port C module.
Table continues on the next page...
Chapter 12 System Integration Module (SIM)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 239