Information

SIM_SCGC6 field descriptions (continued)
Field Description
24
FTM0
FTM0 Clock Gate Control
This bit controls the clock gate to the FTM0 module.
0 Clock disabled
1 Clock enabled
23
PIT
PIT Clock Gate Control
This bit controls the clock gate to the PIT module.
0 Clock disabled
1 Clock enabled
22
PDB
PDB Clock Gate Control
This bit controls the clock gate to the PDB module.
0 Clock disabled
1 Clock enabled
21
USBDCD
USB DCD Clock Gate Control
This bit controls the clock gate to the USB DCD module.
0 Clock disabled
1 Clock enabled
20–19
Reserved
This read-only field is reserved and always has the value zero.
18
CRC
CRC Clock Gate Control
This bit controls the clock gate to the CRC module.
0 Clock disabled
1 Clock enabled
17–16
Reserved
This read-only field is reserved and always has the value zero.
15
I2S
I2S Clock Gate Control
This bit controls the clock gate to the I
2
S module.
0 Clock disabled
1 Clock enabled
14
Reserved
This read-only field is reserved and always has the value zero.
13
Reserved
This read-only field is reserved and always has the value zero.
12
SPI0
SPI0 Clock Gate Control
This bit controls the clock gate to the SPI0 module.
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
242 Freescale Semiconductor, Inc.