Information

SIM_CLKDIV1 field descriptions (continued)
Field Description
15–0
Reserved
This read-only field is reserved and always has the value zero.
12.2.13 System Clock Divider Register 2 (SIM_CLKDIV2)
Address: SIM_CLKDIV2 is 4004_7000h base + 1048h offset = 4004_8048h
Bit 31 30 29 28 27 26 25 24
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8
R
0
W
Reset
0 0 0 0 0 0 0 0
Bit
7 6 5 4 3 2 1 0
R
0
USBDIV USBFRAC
W
Reset
0 0 0 0 0 0 0 0
SIM_CLKDIV2 field descriptions
Field Description
31–4
Reserved
This read-only field is reserved and always has the value zero.
3–1
USBDIV
USB clock divider divisor
This field sets the divide value for the fractional clock divider when the MCGFLLCLK/MCGPLLCLK clock
is the USB clock source (SOPT2[USBSRC] = 1).
Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ]
0
USBFRAC
USB clock divider fraction
This field sets the fraction multiply value for the fractional clock divider when the MCGFLLCLK/
MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1).
Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ]
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
246 Freescale Semiconductor, Inc.