Information

12.2.15 Flash Configuration Register 2 (SIM_FCFG2)
Address: SIM_FCFG2 is 4004_7000h base + 1050h offset = 4004_8050h
Bit 31 30 29 28 27 26 25 24
R
0 MAXADDR0
W
Reset
x* x* x* x* x* x* x* x*
Bit
23 22 21 20 19 18 17 16
R
PFLSH MAXADDR1
W
Reset
x* x* x* x* x* x* x* x*
Bit
15 14 13 12 11 10 9 8
R
0
W
Reset
x* x* x* x* x* x* x* x*
Bit
7 6 5 4 3 2 1 0
R
0
W
Reset
x* x* x* x* x* x* x* x*
* Notes:
Reset value loaded during System Reset from Flash IFR.x = Undefined at reset.•
SIM_FCFG2 field descriptions
Field Description
31
Reserved
This read-only field is reserved and always has the value zero.
30–24
MAXADDR0
Max address block 0
This field concatenated with leading zeros indicates the first invalid address of flash block 0 (program
flash 0).
For example, if MAXADDR0 = 0x20 the first invalid address of flash block 0 is 0x0004_0000. This would
be the MAXADDR0 value for a device with 256 KB program flash in flash block 0.
23
PFLSH
Program flash
For devices with FlexNVM, this bit is always clear.
0 Physical flash block 1 is used as FlexNVM
1 Physical flash block 1 is used as program flash
22–16
MAXADDR1
Max address block 1
This field concatenated with leading zeros plus the FlexNVM base address indicates the first invalid
address of the FlexNVM (flash block 1).
For example, if MAXADDR1 = 0x20 the first invalid address of flash block 1 is 0x4_0000 + 0x1000_0000 .
This would be the MAXADDR1 value for a device with 256 KB FlexNVM.
Table continues on the next page...
Chapter 12 System Integration Module (SIM)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 249