Information

Section Number Title Page
32.4 ANMUX key features...................................................................................................................................................635
32.5 CMP, DAC and ANMUX diagram...............................................................................................................................635
32.6 CMP block diagram......................................................................................................................................................636
32.7 Memory map/register definitions..................................................................................................................................638
32.7.1 CMP Control Register 0 (CMPx_CR0).......................................................................................................639
32.7.2 CMP Control Register 1 (CMPx_CR1).......................................................................................................640
32.7.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................641
32.7.4 CMP Status and Control Register (CMPx_SCR).........................................................................................641
32.7.5 DAC Control Register (CMPx_DACCR)....................................................................................................643
32.7.6 MUX Control Register (CMPx_MUXCR)..................................................................................................643
32.8 CMP functional description..........................................................................................................................................644
32.8.1 CMP functional modes.................................................................................................................................644
32.8.2 Power modes................................................................................................................................................654
32.8.3 Startup and operation...................................................................................................................................655
32.8.4 Low-pass filter.............................................................................................................................................656
32.9 CMP interrupts..............................................................................................................................................................658
32.10 CMP DMA support.......................................................................................................................................................658
32.11 Digital-to-analog converter block diagram...................................................................................................................659
32.12 DAC functional description..........................................................................................................................................659
32.12.1 Voltage reference source select....................................................................................................................659
32.13 DAC resets....................................................................................................................................................................660
32.14 DAC clocks...................................................................................................................................................................660
32.15 DAC interrupts..............................................................................................................................................................660
Chapter 33
Voltage Reference (VREFV1)
33.1 Introduction...................................................................................................................................................................661
33.1.1 Overview......................................................................................................................................................662
33.1.2 Features........................................................................................................................................................662
33.1.3 Modes of Operation.....................................................................................................................................663
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 25