Information

RCM_SRS0 field descriptions (continued)
Field Description
0 Reset not caused by a loss of external clock.
1 Reset caused by a loss of external clock.
1
LVD
Low-voltage detect reset
If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This bit is
also set by POR.
0 Reset not caused by LVD trip or POR
1 Reset caused by LVD trip or POR
0
WAKEUP
Low leakage wakeup reset
Indicates a reset was caused by an enabled LLWU module wakeup source while the chip was in a low
leakage mode. In LLS mode, the RESET pin is the only wakeup source that can cause this reset. Any
enabled wakeup source in a VLLSx mode causes a reset. This bit is cleared by any reset except
WAKEUP.
0 Reset not caused by LLWU module wakeup source
1 Reset caused by LLWU module wakeup source
13.2.2 System Reset Status Register 1 (RCM_SRS1)
This register includes read-only status flags to indicate the source of the most recent
reset. The reset state of these bits depends on what caused the MCU to reset.
NOTE
The reset value of this register depends on the reset source:
• POR (including LVD) — 0x00
• LVD (without POR) — 0x00
• VLLS mode wakeup — 0x00
• Other reset — a bit is set if its corresponding reset source
caused the reset
Address: RCM_SRS1 is 4007_F000h base + 1h offset = 4007_F001h
Bit 7 6 5 4 3 2 1 0
Read 0 0 SACKERR EZPT MDM_AP SW LOCKUP JTAG
Write
Reset
0 0 0 0 0 0 0 0
RCM_SRS1 field descriptions
Field Description
7
Reserved
This read-only field is reserved and always has the value zero.
Table continues on the next page...
Chapter 13 Reset Control Module (RCM)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 255