Information

Section Number Title Page
33.1.4 VREF Signal Descriptions...........................................................................................................................663
33.2 Memory Map and Register Definition..........................................................................................................................664
33.2.1 VREF Trim Register (VREF_TRM)............................................................................................................664
33.2.2 VREF Status and Control Register (VREF_SC)..........................................................................................665
33.3 Functional Description..................................................................................................................................................666
33.3.1 Voltage Reference Disabled, SC[VREFEN] = 0.........................................................................................667
33.3.2 Voltage Reference Enabled, SC[VREFEN] = 1..........................................................................................667
33.4 Initialization/Application Information..........................................................................................................................668
Chapter 34
Programmable Delay Block (PDB)
34.1 Introduction...................................................................................................................................................................669
34.1.1 Features........................................................................................................................................................669
34.1.2 Implementation............................................................................................................................................670
34.1.3 Back-to-back Acknowledgement Connections............................................................................................671
34.1.4 Block Diagram.............................................................................................................................................671
34.1.5 Modes of Operation.....................................................................................................................................673
34.2 PDB Signal Descriptions..............................................................................................................................................673
34.3 Memory Map and Register Definition..........................................................................................................................673
34.3.1 Status and Control Register (PDBx_SC).....................................................................................................674
34.3.2 Modulus Register (PDBx_MOD).................................................................................................................677
34.3.3 Counter Register (PDBx_CNT)...................................................................................................................677
34.3.4 Interrupt Delay Register (PDBx_IDLY)......................................................................................................678
34.3.5 Channel n Control Register 1 (PDBx_CHnC1)...........................................................................................678
34.3.6 Channel n Status Register (PDBx_CHnS)...................................................................................................679
34.3.7 Channel n Delay 0 Register (PDBx_CHnDLY0)........................................................................................680
34.3.8 Channel n Delay 1 Register (PDBx_CHnDLY1)........................................................................................680
34.3.9 Pulse-Out n Enable Register (PDBx_POEN)...............................................................................................681
34.3.10 Pulse-Out n Delay Register (PDBx_POnDLY)...........................................................................................681
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
26 Freescale Semiconductor, Inc.