Information

ARM CPU mode MCU mode
Sleep Wait
Deep Sleep Stop
Accordingly, the ARM CPU documentation refers to sleep and deep sleep, while the
Freescale MCU documentation normally uses wait and stop.
In addition, Freescale MCUs also augment stop, wait, and run modes in a number of
ways. The power management controller (PMC) contains a run and a stop mode
regulator. Run regulation is used in normal run, wait and stop modes. Stop mode
regulation is used during all very low power and low leakage modes. During stop mode
regulation, the bus frequencies are limited in the very low power modes.
The SMC provides the user with multiple power options. The Very Low Power Run
(VLPR) mode can drastically reduce run time power when maximum bus frequency is
not required to handle the application needs. From Normal Run mode, the Run Mode
(RUNM) field can be modified to change the MCU into VLPR mode when limited
frequency is sufficient for the application. From VLPR mode, a corresponding wait
(VLPW) and stop (VLPS) mode can be entered.
Depending on the needs of the user application, a variety of stop modes are available that
allow the state retention, partial power down or full power down of certain logic and/or
memory. I/O states are held in all modes of operation. Several registers are used to
configure the various modes of operation for the device.
The following table describes the power modes available for the device.
Table 14-1. Power modes
Mode Description
RUN The MCU can be run at full speed and the internal supply is fully regulated, that is, in run regulation.
This mode is also referred to as Normal Run mode.
WAIT The core clock to the ARM Cortex-M4 core is shut off. The system clock continues to operate. Bus
clocks, if enabled, continue to operate. Run regulation is maintained.
STOP The core clock and system clock to the ARM Cortex-M4 core are shut off. System clock to other
masters and bus clocks are stopped after all stop acknowledge signals from supporting peripherals
are valid.
VLPR The core, system, bus, and flash clock maximum frequencies are restricted in this mode. See the
Power Management chapter for details about the maximum allowable frequencies.
VLPW The core clock to the ARM Cortex-M4 core is shut off. The system, bus, and flash clocks continue
to operate, although their maximum frequency is restricted. See the Power Management chapter for
details on the maximum allowable frequencies.
VLPS The core clock and system clock to the ARM Cortex-M4 core is shut off. System clock to other
masters and bus clocks are stopped after all stop acknowledge signals from supporting peripherals
are valid.
Table continues on the next page...
Modes of operation
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
262 Freescale Semiconductor, Inc.