Information

Table 14-1. Power modes (continued)
Mode Description
LLS The core clock and system clock to the ARM Cortex-M4 core is shut off. System clock and bus
clocks are stopped after all stop acknowledge signals from supporting peripherals are valid. The
MCU is placed in a low leakage mode by reducing the voltage to internal logic. Internal logic states
are retained.
VLLS3 The core clock and system clock to the ARM Cortex-M4 core is shut off. System clock to other
masters and bus clocks are stopped after all stop acknowledge signals from supporting peripherals
are valid. The MCU is placed in a low leakage mode by powering down the internal logic. All system
RAM contents are retained and I/O states are held. FlexRAM contents are not retained. Internal
logic states are not retained.
VLLS2 The core clock and system clock to the ARM Cortex-M4 core is shut off. System clock to other
masters and bus clocks are stopped after all stop acknowledge signals from supporting peripherals
are valid. The MCU is placed in a low leakage mode by powering down the internal logic and the
system RAM2 partition. The system RAM1 partition contents are retained in this mode. FlexRAM
contents are not retained. Internal logic states are not retained.
1
VLLS1 In ARM architectures, core clock and system clock to the ARM Cortex-M4 core is shut off. System
clock to other masters and bus clocks are stopped after all stop acknowledge signals from
supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the
internal logic and all system RAM. A 32-byte register file (available in all modes) contents are
retained and I/O states held. FlexRAM contents are not retained. Internal logic states are not
retained.
VLLS0 In ARM architectures, core clock and system clock to the ARM Cortex-M4 core is shut off. System
clock to other masters and bus clocks are stopped after all stop acknowledge signals from
supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the
internal logic and all system RAM. A 32-byte register file (available in all modes) contents are
retained and I/O states held. FlexRAM contents are not retained. Internal logic states are not
retained. The 1kHz LPO clock is disabled and the power on reset (POR) circuit can be optionally
enabled using VLLSCTRL[PORPO].
1. See the devices' chip configuration details for the size and location of the system RAM partitions.
14.3 Memory map and register descriptions
Details follow about the registers related to the system mode controller.
Different SMC registers reset on different reset types. Each register's description provides
details. For more information about the types of reset on this chip, refer to the Reset
section details.
SMC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_E000 Power Mode Protection Register (SMC_PMPROT) 8 R/W 00h 14.3.1/264
4007_E001 Power Mode Control Register (SMC_PMCTRL) 8 R/W 00h 14.3.2/265
4007_E002 VLLS Control Register (SMC_VLLSCTRL) 8 R/W 03h 14.3.3/267
4007_E003 Power Mode Status Register (SMC_PMSTAT) 8 R 01h 14.3.4/268
Chapter 14 System Mode Controller
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 263