Information

SMC_PMPROT field descriptions (continued)
Field Description
2
Reserved
This read-only field is reserved and always has the value zero.
1
AVLLS
Allow very low leakage stop mode
Provided the appropriate control bits are set up in PMCTRL, this write once bit allows the MCU to enter
any very low leakage stop mode (VLLSx).
0 Any VLLSx mode is not allowed
1 Any VLLSx mode is allowed
0
Reserved
This read-only field is reserved and always has the value zero.
14.3.2 Power Mode Control Register (SMC_PMCTRL)
The PMCTRL register controls entry into low power run and stop modes, provided that
the selected power mode is allowed via an appropriate setting of the protection
(PMPROT) register.
NOTE
This register is reset on Chip POR not VLLS and by reset types
that trigger Chip POR not VLLS. It is unaffected by reset types
that do not trigger Chip POR not VLLS. See the Reset section
details. for more information.
Address: SMC_PMCTRL is 4007_E000h base + 1h offset = 4007_E001h
Bit 7 6 5 4 3 2 1 0
Read
LPWUI RUNM
0 STOPA
STOPM
Write
Reset
0 0 0 0 0 0 0 0
SMC_PMCTRL field descriptions
Field Description
7
LPWUI
Low Power Wake Up on Interrupt
Causes the SMC to exit to normal RUN mode when any active MCU interrupt occurs while in a VLP mode
(VLPR, VLPW or VLPS).
NOTE: If VLPS mode was entered directly from RUN mode, the SMC will always exit back to normal
RUN mode regardless of the LPWUI setting.
NOTE: LPWUI should only be modified while the system is in RUN mode i.e. when PMSTAT=RUN.
0 The system remains in a VLP mode on an interrupt
1 The system exits to normal RUN mode on an interrupt
Table continues on the next page...
Chapter 14 System Mode Controller
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 265