Information

WAIT
STOP
RUN
LLS
VLLSx
VLPS
VLPR
VLPW
Any reset
4
6
7
3
1
2
8
10
11
9
5
Figure 14-5. Power mode state diagram
The following table defines triggers for the various state transitions shown in the previous
figure.
Table 14-7. Power mode transition triggers
Transition # From To Trigger conditions
1 RUN WAIT Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
clear, controlled in System Control Register in ARM core.
See note.
1
WAIT RUN Interrupt or Reset
Table continues on the next page...
Chapter 14 System Mode Controller
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 269