Information

Table 14-7. Power mode transition triggers (continued)
Transition # From To Trigger conditions
2 RUN STOP PMCTRL[RUNM]=00, PMCTRL[STOPM]=000
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
set, which is controlled in System Control Register in ARM
core.
See note.
1
STOP RUN Interrupt or Reset
3 RUN VLPR Reduce system, bus and core frequency to 2 MHz or less,
Flash access limited to 1 MHz.
Set PMPROT[AVLP]=1, PMCTRL[RUNM]=10.
VLPR RUN Set PMCTRL[RUNM]=00 or
Interrupt with PMCTRL[LPWUI] =1 or
Reset.
4 VLPR VLPW Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
clear, which is controlled in System Control Register in ARM
core.
See note.
1
VLPW VLPR Interrupt with PMCTRL[LPWUI]=0
5 VLPW RUN Interrupt with PMCTRL[LPWUI]=1 or
Reset
6 VLPR VLPS PMCTRL[STOPM]=000 or 010,
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
set, which is controlled in System Control Register in ARM
core.
See note.
1
VLPS VLPR Interrupt with PMCTRL[LPWUI]=0
NOTE: If VLPS was entered directly from RUN, hardware
will not allow this transition and will force exit back to
RUN
7 RUN VLPS PMPROT[AVLP]=1, PMCTRL[STOPM]=010,
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
set, which is controlled in System Control Register in ARM
core.
See note.
1
VLPS RUN Interrupt with PMCTRL[LPWUI]=1 or
Interrupt with PMCTRL[LPWUI]=0 and VLPS mode was
entered directly from RUN or
Reset
Table continues on the next page...
Functional Description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
270 Freescale Semiconductor, Inc.