Information

System
Mode
Controller
(SMC)
System
Power
(PMC)
Low
-
Leakage
Wakeup
(LLWU)
System
Clocks
(MCG)
LP exit
Flash
CPU
LP exit
Clock
Control
Module
(CCM)
Module
Memory
Bus masters low power bus (non-CPU)
Bus slaves low power bus
Stop/Wait
CCM low power bus
MCG enable
PMC low power bus
Flash low power bus
Reset
Control
(RCM)
Module
Figure 14-6. Low-power system components and connections
14.4.2.1 Stop mode entry sequence
Entry into a low-power stop mode (Stop, VLPS, LLS, VLLSx) is initiated by CPU
execution of the WFI instruction. After the instruction is executed, the following
sequence occurs:
1. The CPU clock is gated off immediately.
2. Requests are made to all non-CPU bus masters to enter Stop mode.
3. After all masters have acknowledged they are ready to enter Stop mode, requests are
made to all bus slaves to enter Stop mode.
4. After all slaves have acknowledged they are ready to enter Stop mode, all system and
bus clocks are gated off.
5. Clock generators are disabled in the MCG.
6. The on-chip regulator in the PMC and internal power switches are configured to
meet the power consumption goals for the targeted low-power mode.
Functional Description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
272 Freescale Semiconductor, Inc.