Information

In VLLS, the on-chip voltage regulator is in its stop-regulation state while most digital
logic is powered off.
In VLLS, configure the LLWU module to enable the desired wakeup sources. The
available wakeup sources in VLLS are detailed LLWU's chip configuration details for
this device.
When entering VLLS, each I/O pin is latched as configured before executing VLLS.
Because all digital logic in the MCU is powered off, all port and peripheral data is lost
during VLLS. This information must be restored before ACKISO bit in the PMC is set.
An asserted RESET pin will cause an exit from any VLLS mode, returning the device to
normal RUN mode. When exiting VLLS via the RESET pin, the PIN and WAKEUP bits
are set in the SRS0 register of the reset control module (RCM).
14.4.6 Debug in low power modes
When the MCU is secure, the device disables/limits debugger operation. When the MCU
is unsecure, the ARM debugger can assert two power-up request signals:
• System power up, via SYSPWR in the Debug Port Control/Stat register
• Debug power up, via CDBGPWRUPREQ in the Debug Port Control/Stat register
When asserted while in RUN, WAIT, VLPR, or VLPW, the mode controller drives a
corresponding acknowledge for each signal, that is, both CDBGPWRUPACK and
CSYSPWRUPACK. When both requests are asserted, the mode controller handles
attempts to enter STOP and VLPS by entering an emulated stop state. In this emulated
stop state:
• the regulator is in run regulation,
• the MCG-generated clock source is enabled,
• all system clocks, except the core clock, are disabled,
• the debug module has access to core registers, and
• access to the on-chip peripherals is blocked.
No debug is available while the MCU is in LLS or VLLS modes. LLS is a state-retention
mode and all debug operation can continue after waking from LLS, even in cases where
system wakeup is due to a system reset event.
Entering into a VLLS mode causes all of the debug controls and settings to be powered
off. To give time to the debugger to sync with the MCU, the MDM AP Control Register
includes a Very-Low-Leakage Debug Request (VLLDBGREQ) bit that is set to configure
Chapter 14 System Mode Controller
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 279