Information

• The low voltage detect flag (LVDF) operates in a level sensitive manner. The LVDF
bit is set when the supply voltage falls below the selected trip point (VLVD). The
LVDF bit is cleared by writing one to the LVDACK bit, but only if the internal
supply has returned above the trip point; otherwise, the LVDF bit remains set.
• The low voltage warning flag (LVWF) operates in a level sensitive manner. The
LVWF bit is set when the supply voltage falls below the selected monitor trip point
(VLVW). The LVWF bit is cleared by writing one to the LVWACK bit, but only if
the internal supply has returned above the trip point; otherwise, the LVWF bit
remains set.
15.3.1 LVD reset operation
By setting the LVDRE bit, the LVD generates a reset upon detection of a low voltage
condition. The low voltage detection threshold is determined by the LVDV bits. After an
LVD reset occurs, the LVD system holds the MCU in reset until the supply voltage rises
above this threshold. The LVD bit in the SRS register is set following an LVD or power-
on reset.
15.3.2 LVD interrupt operation
By configuring the LVD circuit for interrupt operation (LVDIE set and LVDRE clear),
LVDSC1[LVDF] is set and an LVD interrupt request occurs upon detection of a low
voltage condition. The LVDF bit is cleared by writing one to the LVDSC1[LVDACK]
bit.
15.3.3 Low-voltage warning (LVW) interrupt operation
The LVD system contains a low-voltage warning flag (LVWF) to indicate that the supply
voltage is approaching, but is above, the LVD voltage. The LVW also has an interrupt,
which is enabled by setting the LVDSC2[LVWIE] bit. If enabled, an LVW interrupt
request occurs when the LVWF is set. LVWF is cleared by writing one to the
LVDSC2[LVWACK] bit.
The LVDSC2[LVWV] bits select one of four trip voltages:
• Highest: V
LVW4
• Two mid-levels: V
LVW3
and V
LVW2
• Lowest: V
LVW1
Low-voltage detect (LVD) system
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
282 Freescale Semiconductor, Inc.