Information

15.4 I/O retention
When in LLS mode, the I/O pins are held in their input or output state. Upon wakeup, the
PMC is re-enabled, goes through a power up sequence to full regulation, and releases the
logic from state retention mode. The I/O are released immediately after a wakeup or reset
event. In the case of LLS exit via a RESET pin, the I/O default to their reset state.
When in VLLS modes, the I/O states are held on a wakeup event (with the exception of
wakeup by reset event) until the wakeup has been acknowledged via a write to the
ACKISO bit. In the case of VLLS exit via a RESET pin, the I/O are released and default
to their reset state. In this case, no write to the ACKISO is needed.
15.5 Memory map and register descriptions
PMC register details follow.
NOTE
Different portions of PMC registers are reset only by particular
reset types. Each register's description provides details. For
more information about the types of reset on this chip, refer to
the Reset section details.
PMC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_D000
Low Voltage Detect Status And Control 1 register
(PMC_LVDSC1)
8 R/W 10h 15.5.1/283
4007_D001
Low Voltage Detect Status And Control 2 register
(PMC_LVDSC2)
8 R/W 00h 15.5.2/285
4007_D002 Regulator Status And Control register (PMC_REGSC) 8 R/W 04h 15.5.3/286
15.5.1 Low Voltage Detect Status And Control 1 register
(PMC_LVDSC1)
This register contains status and control bits to support the low voltage detect function.
This register should be written during the reset initialization program to set the desired
controls even if the desired settings are the same as the reset settings.
Chapter 15 Power Management Controller
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 283