Information

While the device is in the very low power or low leakage modes, the LVD system is
disabled regardless of LVDSC1 settings. To protect systems that must have LVD always
on, configure the SMC's power mode protection register (PMPROT) to disallow any very
low power or low leakage modes from being enabled.
See the device's data sheet for the exact LVD trip voltages.
NOTE
The LVDV bits are reset solely on a POR Only event. The
register's other bits are reset on Chip Reset Not VLLS. For
more information about these reset types, refer to the Reset
section details.
Address: PMC_LVDSC1 is 4007_D000h base + 0h offset = 4007_D000h
Bit 7 6 5 4 3 2 1 0
Read LVDF 0
LVDIE LVDRE
0
LVDV
Write LVDACK
Reset
0 0 0 1 0 0 0 0
PMC_LVDSC1 field descriptions
Field Description
7
LVDF
Low-Voltage Detect Flag
This read-only status bit indicates a low-voltage detect event.
0 Low-voltage event not detected
1 Low-voltage event detected
6
LVDACK
Low-Voltage Detect Acknowledge
This write-only bit is used to acknowledge low voltage detection errors. Write 1 to clear LVDF. Reads
always return 0.
5
LVDIE
Low-Voltage Detect Interrupt Enable
Enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling)
1 Request a hardware interrupt when LVDF = 1
4
LVDRE
Low-Voltage Detect Reset Enable
This write-once bit enables LVDF events to generate a hardware reset. Additional writes are ignored.
0 LVDF does not generate hardware resets
1 Force an MCU reset when LVDF = 1
3–2
Reserved
This read-only field is reserved and always has the value zero.
1–0
LVDV
Low-Voltage Detect Voltage Select
Selects the LVD trip point voltage (V
LVD
).
Table continues on the next page...
Memory map and register descriptions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
284 Freescale Semiconductor, Inc.