Information

PMC_LVDSC1 field descriptions (continued)
Field Description
00 Low trip point selected (V
LVD
= V
LVDL
)
01 High trip point selected (V
LVD
= V
LVDH
)
10 Reserved
11 Reserved
15.5.2 Low Voltage Detect Status And Control 2 register
(PMC_LVDSC2)
This register contains status and control bits to support the low voltage warning function.
While the device is in the very low power or low leakage modes, the LVD system is
disabled regardless of LVDSC2 settings.
See the device's data sheet for the exact LVD trip voltages.
NOTE
The LVW trip voltages depend on LVWV and LVDV bits.
NOTE
The LVWV bits are reset solely on a POR Only event. The
register's other bits are reset on Chip Reset Not VLLS. For
more information about these reset types, refer to the Reset
section details.
Address: PMC_LVDSC2 is 4007_D000h base + 1h offset = 4007_D001h
Bit 7 6 5 4 3 2 1 0
Read LVWF 0
LVWIE
0
LVWV
Write LVWACK
Reset
0 0 0 0 0 0 0 0
PMC_LVDSC2 field descriptions
Field Description
7
LVWF
Low-Voltage Warning Flag
This read-only status bit indicates a low-voltage warning event. LVWF is set when V
Supply
transitions
below the trip point, or after reset and V
Supply
is already below V
LVW
.
0 Low-voltage warning event not detected
1 Low-voltage warning event detected
6
LVWACK
Low-Voltage Warning Acknowledge
This write-only bit is used to acknowledge low voltage warning errors. Write 1 to clear LVWF. Reads
always return 0.
Table continues on the next page...
Chapter 15 Power Management Controller
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 285