Information

Section Number Title Page
35.4.13 Software output control................................................................................................................................784
35.4.14 Deadtime insertion.......................................................................................................................................786
35.4.15 Output mask.................................................................................................................................................789
35.4.16 Fault control.................................................................................................................................................790
35.4.17 Polarity control.............................................................................................................................................793
35.4.18 Initialization.................................................................................................................................................794
35.4.19 Features priority...........................................................................................................................................794
35.4.20 Channel trigger output.................................................................................................................................795
35.4.21 Initialization trigger......................................................................................................................................796
35.4.22 Capture Test mode.......................................................................................................................................798
35.4.23 DMA............................................................................................................................................................799
35.4.24 Dual Edge Capture mode.............................................................................................................................800
35.4.25 Quadrature Decoder mode...........................................................................................................................807
35.4.26 BDM mode...................................................................................................................................................812
35.4.27 Intermediate load..........................................................................................................................................813
35.4.28 Global time base (GTB)...............................................................................................................................815
35.5 Reset overview..............................................................................................................................................................816
35.6 FTM Interrupts..............................................................................................................................................................818
35.6.1 Timer Overflow Interrupt.............................................................................................................................818
35.6.2 Channel (n) Interrupt....................................................................................................................................818
35.6.3 Fault Interrupt..............................................................................................................................................818
Chapter 36
Periodic Interrupt Timer (PIT)
36.1 Introduction...................................................................................................................................................................819
36.1.1 Block diagram..............................................................................................................................................819
36.1.2 Features........................................................................................................................................................820
36.2 Signal description..........................................................................................................................................................820
36.3 Memory map/register description.................................................................................................................................821
36.3.1 PIT Module Control Register (PIT_MCR)..................................................................................................822
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 29