Information

LLWU_F2 field descriptions (continued)
Field Description
2
WUF10
Wakeup Flag For LLWU_P10
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To
clear the flag write a one to WUF10.
0 LLWU_P10 input was not a wakeup source
1 LLWU_P10 input was a wakeup source
1
WUF9
Wakeup Flag For LLWU_P9
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To
clear the flag write a one to WUF9.
0 LLWU_P9 input was not a wakeup source
1 LLWU_P9 input was a wakeup source
0
WUF8
Wakeup Flag For LLWU_P8
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To
clear the flag write a one to WUF8.
0 LLWU_P8 input was not a wakeup source
1 LLWU_P8 input was a wakeup source
16.3.8 LLWU Flag 3 register (LLWU_F3)
LLWU_F3 contains the wakeup flags indicating which internal wakeup source caused the
MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt
flow. For VLLS, this is the source causing the MCU reset flow.
For internal peripherals that are capable of running in a low-leakage power mode, such as
RTC or CMP modules, the flag from the associated peripheral is accessible as the
MWUFx bit. The flag will need to be cleared in the peripheral instead of writing a 1 to
the MWUFx bit.
NOTE
This register is reset on Chip Reset not VLLS and by reset
types that trigger Chip Reset not VLLS. It is unaffected by reset
types that do not trigger Chip Reset not VLLS. See the
Introduction details for more information.
Address: LLWU_F3 is 4007_C000h base + 7h offset = 4007_C007h
Bit 7 6 5 4 3 2 1 0
Read MWUF7 MWUF6 MWUF5 MWUF4 MWUF3 MWUF2 MWUF1 MWUF0
Write
Reset
0 0 0 0 0 0 0 0
Chapter 16 Low-Leakage Wakeup Unit (LLWU)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 303