Information

16.4 Functional description
This on-chip peripheral module is called a low-leakage wakeup unit (LLWU) module
because it allows internal peripherals and external input pins as a source of wakeup from
low-leakage modes. It is operational only in LLS and VLLSx modes.
The LLWU module contains pin enables for each external pin and internal module. For
each external pin, the user can disable or select the edge type for the wakeup. Type
options are:
• Falling-edge
• Rising-edge
• Either-edge
When an external pin is enabled as a wakeup source, the pin must be configured as an
input pin.
The LLWU implements optional 3-cycle glitch filters, based on the LPO clock. A
detected external pin, either wakeup or
RESET, is required to remain asserted until the
enabled glitch filter times out. Additional latency of up to 2 cycles is due to
synchronization, which results in a total of up to 5 cycles of delay before the detect
circuit alerts the system to the wakeup or reset event when the filter function is enabled.
Two wakeup detect filters are available to detect up to two external pins. A separate reset
filter is on the RESET pin. Glitch filtering is not provided on the internal modules.
For internal module wakeup operation, the WUMEx bit enables the associated module as
a wakeup source.
16.4.1 LLS mode
Wakeup events triggered from either an external pin input or an internal module input
result in a CPU interrupt flow to begin user code execution.
An LLS reset event due to RESET pin assertion causes an exit via a system reset. State
retention data is lost, and the I/O states return to their reset state. The
RCM_SRS[WAKEUP] and RCM_SRS[PIN] bits are set and the system executes a reset
flow before CPU operation begins with a reset vector fetch.
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
308 Freescale Semiconductor, Inc.