Information

16.4.2 VLLS modes
In the case of a wakeup due to external pin or internal module wakeup, recovery is
always via a reset flow and the RCM_SRS[WAKEUP] is set indicating the low-leakage
mode was active. State retention data is lost and I/O will be restored after
PMC_REGSC[ACKISO] has been written.
A VLLS exit event due to RESET pin assertion causes an exit via a system reset. State
retention data is lost and the I/O states immediately return to their reset state. The
RCM_SRS[WAKEUP] and RCM_SRS[PIN] bits are set and the system executes a reset
flow before CPU operation begins with a reset vector fetch.
16.4.3 Initialization
For an enabled peripheral wakeup input, the peripheral flag must be cleared by software
before entering LLS or VLLSx mode to avoid an immediate exit from the mode.
Flags associated with external input pins, filtered and unfiltered, must also be cleared by
software prior to entry to LLS or VLLSx mode.
After enabling an external pin filter or changing the source pin, wait at least 5 LPO clock
cycles before entering LLS or VLLSx mode to allow the filter to initialize.
NOTE
The signal selected as a wakeup source pin must be a digital
pin, as selected in the pin mux control.
Chapter 16 Low-Leakage Wakeup Unit (LLWU)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 309